Necker Cubicle

Check this out.. This entry was posted in Uncategorized . Bookmark the permalink .

“It’s so simple to be wise. Just think of something stupid to say and then don’t say it.” But I always say.. This entry was posted in Uncategorized . Bookmark the permalink .

Wow, I registered a project for the google summer of code. And for those who know how lazy I am, don’t be surprised, it’s also my academic main project! (I have no other way but to do it) The proposal was written today afternoon at about 3.00 pm and didn’t spend much time over it as I need to send it today itself (it was supposed to be the final day for accepting proposals; they postponed it to 26th now). Pramode Sir verified it and added some points more. And the mentor organization under which the project goes is ‘The Free software initiative of Japan”. Internet is an amazing technology – just after an hour I had a comment from the Japanese mentor team, asking about the project. (The project is not yet approved by the SOC people :D) Earlier today I was busy preparing my seminar report and that was a really dumb job. I was trying each and every magical spells I know to find out those materials I collected at the time of seminar. Anyways, the whole report is ready to be submitted now...

My heart has two auricles and two ventricles….. This entry was posted in Uncategorized . Bookmark the permalink .

Verilog is a hardware description language (HDL) that one could easily learn and use because it looks like C language in syntax – the control flow statements like if and while, language operators and their precedence etc are similar to that of C. The language differs from the conventional programming language as the execution of statements is not strictly linear. Oh!! I forget to tell what a HDL is.. HDL is any language used for the formal description of electronic circuits. It describes the circuits operation and through simulations we can check if the circuit is behaving as we intend. With that the formal introduction of this article ends. Now let us do some Verilog-ing.             As a first step one need to design the circuit and then he has to decide how to use Verilog to describe it.   For the time being let me focus on gate level modeling.   X = AB + C ::   this is what I want to simulate using Verilog. Th...